Field Effect Transistors (FETs) are ubiquitous devices used in a wide array of applications. Certain applications require FETs which can handle large voltages. For example, RF switches in cell phones require FETs which can sustain more than 20 volts between the source and drain. Power amplifiers in wireless base stations often require FETs which can sustain more than 50 volts between source and drain and between the gate and drain.
FETs are transistors where the resistance between the source and drain (RSD) is modulated by a gate voltage. FIG. 1 shows a typical GaAs FET 100. The FET illustrated in FIG. 1 has a source contact 105 a drain contact 110 and a gate contact 115. Source contact 105 is in electrical contact with source 120 and drain contact 110 is in electrical contact with drain 125. The FET is formed on a semi-insulating GaAs substrate 145 on which is formed an undoped GaAs buffer layer 140. The device 100 also has a barrier layer 135 formed between the channel 130 and the source 120, drain 125 and gate 115.
When the gate voltage is high enough that the channel isn't fully depleted of charge, the device is in the on-state. In this on-state, RSD(on) is low and current flows from the source 120 through the device channel 130 to the drain 125. When the gate voltage is low enough that the channel is depleted of charge, the device is said to be in the off-state. In the off-state, RSD(off) is high and little or no current flows through the channel 130.
FIG. 1 is a GaAs MESFET with a semiconducting barrier layer. The semiconducting barrier layer has a higher band-gap energy than that of the underlying channel and is typically used to help reduce gate leakage current. The gate 115 is a Schottky barrier metal that contacts the barrier layer 135 to provide a Schottky insulating junction between the gate and the channel. The passivation layer 150 is deposited between the gate 115 and drain 125 and between the source 120 and gate 115 to reduce surface states in these regions. Surface states lead to undesirable device performance along with stability and reliability problems. A typical surface passivation layer is SiO2. Silicon nitride (SiN) is another example of a typical passivation layer.
Typical semiconductor substrates used to form power transistors are silicon (Si) and large band-gap III-V compound semiconductors. Gallium arsenide (GaAs) and gallium nitride (GaN) are examples of the materials referred to as “III-V” materials herein. III-V substrates have several desirable material properties for use in power FETs when compared to Si. These properties include high electron mobility (which leads to improved high frequency performance and lower RSD(on)) and higher bandgap energies (which lead to lower impact ionization and thus higher BV).
Si-based FETs are widely used in power amplifiers for base-stations that require high output power with a corresponding drain to source breakdown voltage (BVDS(off)) that is greater than 60 volts, but have higher RSD and lower maximum power gain frequency (fmax) compared to GaAs FETs. These silicon devices are typically Si LDMOS transistors.
GaAs FETs are typically used in applications when higher speed or lower RSD(on) is required but BVDS need not be as high (e.g. when the off-state breakdown voltage BVDS(off) is about 20 volts). Metal-Semiconductor-FETs (MESFETs) and High-Electron-Mobility-Transistors (HEMTs) are examples of these devices. Examples of such applications are RF switches and lower power amplifiers used in mobile handsets.
However, in any RF power amplifier application it is desirable either to increase BVDS without increasing RSD(on) or to reduce RSD(on) without reducing BVDS. There are many known approaches for reducing the peak electrostatic field of FETs for use in high power applications to address this objective. One approach is a device known as the RESURF (for reduced surface field) device. RESURF devices are described in Karmalkar, S., et al., “RESURF ALGaN/GaN HEMT for High Power Switching,” IEEE Electron Letters, Vol. 22., No. 8 (August 2001). RESURF devices have a p-type region formed below the channel region. The purpose of the p-doped region is to deplete the channel charge when the drain bias is high in order to reduce the peak field in the drift region.
The channel charge can also be depleted by a metal field-plate or overlapping gate. The field plate is placed over the insulator between the gate and the drain. The field plate 155 is illustrated in FIG. 1 and is also described in Asano, K. et al., “Novel High Power AlGaAs HFET with a Field-Modulating Plate Operated at 35 V Drain Voltage,” IEDM, pp. 59–61 (1998). The field plate 155 is placed in the drift region 160 of the device and is electrically connected to the gate or other voltage source (electrical interconnection not shown in FIG. 1). However, there is a physical gap between the gate electrode 115 and the field plate 155. As discussed in Asano et al, the field plate reduces the peak electric field near the gate edge and therefore increases the breakdown voltage of the device. Specifically, Asano et al. reports an increase in BVGD from 30 V to 47 V and attributes that increase to the presence of the field plate.
FIG. 2 is a prior art MESFET 200 in which the field plate is configured as an overlapping gate 255. Such a device is described in Chen, Chang-Lee et al. “High-Breakdown Voltage MESFET with a low temperature-grown GaAs Passivation and Overlapping Gate Structure,” IEEE EDL, Vol. 13 (No. 6) (1992). Chen, Chang-Lee et al. reports an increase in both BVGD (from 25 to 35) and BVDS (from 22 to 37) and attributes the increase to the presence of the overlapping gate in the MESFET. The device in FIG. 2 is otherwise identical to the device in FIG. 1 (with one other exception—the device in FIG. 2 does not have a barrier layer).
However, even with the increases in BV reported above, the reported BV for the devices with field plates/over-lapping gates is still far below the BV of silicon-based laterally diffused MOS (LDMOS) devices (i.e. BV of up to 80 volts).
Other alternatives to the above devices have been proposed. A MISFET device 300 is illustrated in FIG. 3. MISFET 300 is very similar to MESFET 100 (FIG. 1) except for the fact that the gate 315 in MISFET 300 is formed on an insulating barrier layer 350. This barrier layer is also known as a gate insulating layer. Also, MISFET 300 does not have a field plate or overlapping gate.
The barrier layer 350 of MISFET 300 is a low temperature grown (LTG) oxide. However, because the oxide is formed from a III-V material (GaAs) the oxide has too many interface states under the gate 315. These interface states cause undesirable trap-induced effects.
An alternative to the LTG oxide depicted in FIG. 3 was proposed in Ye, P., et al., “GaAs MOSFET With Oxide Gate Dielectric Grown by Atomic Layer Deposition,” IEEE EDL, Vol. 24, No. 4, p. 209–211 (2003). The insulator material described in this reference was aluminum oxide (Al2O3) and it was formed on a GaAs substrate. Ye et al. report a breakdown field as high as 9 MV/cm for the device depicted in FIG. 3. The higher breakdown field is due to the fact that the bandgap energy for Al2O3 is 8 eV compared to 1.4 eV for the LTG GaAs. The insulator material described in this reference had a lower interface state density than the previously described III-V gate oxides.
However, merely inserting a gate oxide into the device, even if that device is the above-described Al2O3 formed by ALD, is not a global solution to increasing the BV for III-V devices. This is because there are multiple sources of BV for these devices.
Accordingly III-VIII-V devices with improved resistance to BV are still sought.